AI Agents Generate Better Hardware Code Together

As semiconductor companies race to develop faster, more efficient chips, the process of writing hardware description language (HDL) code has become a critical bottleneck. This specialized programming, used to design the digital circuits that power everything from smartphones to supercomputers, requires precise timing constraints and concurrent behavior specifications that challenge even experienced engineers. Now, researchers have developed a collaborative AI system that generates more accurate HDL code by combining multiple artificial intelligence agents in a structured framework that prevents errors from propagating through the design process.

The key finding from this research is that a mixture-of-agents approach, where different AI models work together on hardware design tasks, produces significantly better results than individual AI systems. The framework, called V ERI M OA, achieves 15-30% improvements in code generation accuracy across standard benchmarks compared to existing methods. Most remarkably, it achieves these gains without requiring costly retraining of the underlying AI models, making advanced hardware design automation accessible to organizations with limited computational resources.

The methodology employs a layered architecture where multiple AI agents operate in parallel at each stage of the code generation process. The system includes three types of specialized agents: baseline agents that work directly from hardware specifications, C++-guided agents that leverage high-level programming concepts, and Python-guided agents that utilize expressive algorithmic constructs. Rather than having each layer depend only on the immediately preceding results—which can amplify errors—the framework maintains a global cache of all intermediate outputs and selects only the highest-quality candidates for subsequent processing. This quality-guided caching ensures that later stages build upon the best available solutions rather than propagating mistakes.

Results from comprehensive testing on VerilogEval and RTLLM 2.0 benchmarks demonstrate the framework's effectiveness. With the Qwen2.5-7B model, V ERI M OA achieved 56.44% Pass@1 accuracy on VerilogEval, compared to 32.81% for the next best non-training method—a 23.63 percentage point improvement. The system also matched or exceeded the performance of fine-tuned models despite requiring no specialized training. For example, V ERI M OA with Qwen2.5-Coder-32B reached 73.31% Pass@1, surpassing the 66.28% achieved by VeriRL-CodeQwen2.5, a model specifically fine-tuned for hardware design tasks. The research team's analysis showed that the quality-guided caching mechanism was particularly crucial, contributing 11.93 percentage points of improvement with the Qwen2.5-7B model compared to standard approaches.

This advancement matters because it could dramatically accelerate hardware development cycles while reducing costs. Semiconductor design typically requires extensive human expertise and verification, with even small errors potentially costing millions in redesigns and delayed product launches. By enabling more reliable automated code generation, the framework could help chip manufacturers bring new products to market faster while maintaining quality standards. The approach is particularly valuable for smaller companies and research institutions that lack the resources for extensive AI model retraining but still need access to state-of-the-art design automation.

The research acknowledges several limitations. The framework's performance still depends on the underlying AI models' capabilities, and while it significantly reduces error propagation, it doesn't eliminate all inaccuracies. The current implementation focuses on specific types of digital circuits, and its effectiveness on more complex or novel hardware designs remains to be fully explored. Additionally, the computational requirements, while lower than retraining entire models, still necessitate substantial processing power for the multiple parallel agents and quality evaluations.