AI Designs Faster Computer Chips from Scratch

A new artificial intelligence system can design high-speed computer chips from the ground up, bypassing traditional s that rely on modifying existing designs. This approach, developed by researchers from Shanghai Jiao Tong University and the Technical University of Munich, uses a generative AI model called PrefixGPT to create optimized prefix adders—critical arithmetic components used in applications like signal processing and AI hardware. Unlike previous AI techniques that refine existing structures and often struggle with design rule violations, PrefixGPT generates valid circuit topologies directly, eliminating repair steps and initialization bias that have long hampered automated hardware design. The model discovered a new optimal design with a 7.7% improved area-delay product and reduced average performance metrics by up to 79.1% compared to state-of-the-art s, demonstrating a leap in both efficiency and robustness for electronic design automation.

The key finding is that PrefixGPT consistently produces superior circuit designs across various starting conditions, whereas existing s show dramatic fluctuations or even failure. As illustrated in Figure 1 of the paper, when optimizing 32-bit adders, two leading s—PrefixRL and ArithTree—yielded inconsistent or no solution at all depending on whether they started from manual designs like Sklansky, Kogge-Stone, or Brent-Kung adders, or from random initializations. In contrast, PrefixGPT was robust, finding better designs in all cases, with depth and size (approximating delay and area) consistently lower. This overcomes a major limitation where prior AI-based optimization frameworks were highly sensitive to initial designs, often trapping them in suboptimal regions of the exponentially large design space. The model's ability to generate valid designs by construction ensures every output adheres to strict hardware rules, avoiding the costly and inconvenient repair steps that plague refinement-based approaches.

Ologically, the researchers reformulated prefix adder optimization as a sequence generation problem, enabling the use of a generative pre-trained Transformer (GPT) model. They represented an adder's topology as a two-dimensional coordinate sequence derived from a binary matrix, where each coordinate corresponds to a node in the circuit graph. To ensure validity, they recast the design rules—input, output, and merge rules—into a dynamic legality mask applied during generation, which filters out invalid choices at each step. PrefixGPT features a customized decoder-only Transformer architecture with spatial coordinate embedding and a two-head backbone for predicting row and column coordinates separately. The model was first pre-trained on a corpus of one million randomly synthesized valid prefix adders to learn design rules, then fine-tuned using reinforcement learning to optimize the area-delay product, a common metric balancing circuit size and speed.

, Detailed across multiple experiments, show PrefixGPT's superior performance and exploration quality. In Table 1, PrefixGPT achieved the best prefix graph sizes under strict depth limits for bit-widths of 16, 24, 32, and 48, with a maximum size reduction of 59.1% on 48-bit adders with Kogge-Stone initialization. Prior s often produced invalid designs or much larger sizes under tight constraints. For area-delay product (ADP), Figure 4 reveals that PrefixGPT achieved a minimum ADP of 31.13 µm²·ns for 16-bit adders, outperforming a generative baseline called PrefixLLM, and at 48-bit, it discovered a design with a 7.7% improvement over ArithTree and a 15.1% improvement over PrefixRL. Averaged over all designs, PrefixGPT reduced mean ADP by 71.9% for 32-bit adders and 79.1% for 48-bit adders compared to ArithTree, with substantially lower variance indicating greater stability. Figure 5 further demonstrates that even under random initializations, PrefixGPT's designs closely match its global Pareto frontier, often surpassing the best from other s.

Of this research extend beyond adder design, suggesting that GPT-style models can master complex hardware design principles and apply them for efficient optimization in structured domains. By generating valid designs from scratch, PrefixGPT avoids the initialization bias and repair issues of refinement-based s, potentially accelerating the development of faster and more area-efficient circuits for compute-intensive applications like AI and signal processing. The model's robustness and speed—generating one design in approximately 7 milliseconds for a 32-bit task—make it practical for real-world electronic design automation, where exploring vast design spaces quickly is crucial. This approach could inspire similar applications in other hardware components, leveraging generative AI to push the boundaries of what's possible in circuit optimization without human intervention.

Limitations of the work include the model's reliance on a restriction that simplifies sequence generation by fixing the more significant parent of merge nodes, which may sacrifice some optimality, as noted in the paper. The researchers plan to relax this restriction in future work. Additionally, pre-training was conducted on sequences up to n=48 due to GPU memory constraints, though the model can adapt to smaller bit-widths instantly. The fine-tuning process, while efficient, involves a best-design retrieval mechanism that may influence , though ablation studies showed its removal primarily affects stability rather than average performance. The paper also highlights that the generative baseline, PrefixLLM, only scales to 16-bit adders with long generation times, limiting direct comparison, and further validation on more complex circuit types beyond adders is needed to generalize .