New Method Speeds Up Circuit Simulation Dramatically

Electric circuits are fundamental to modern technology, powering everything from consumer electronics and communication networks to medical devices and industrial control systems. Simulating these circuits allows engineers to predict behavior, optimize performance, and reduce development costs, but traditional s can be slow, especially for complex systems. A new study introduces two innovative approaches that significantly accelerate this process, making simulations faster and more efficient for practical applications.

The researchers developed a parallel Gauss-Jordan elimination algorithm that splits the matrix representing the circuit into batches of rows, assigning each batch to a separate processor on a multicore CPU. To minimize synchronization delays between processors, they introduced a separate pivot matrix that stores pivot rows in a read-only format, allowing all processors to access them without waiting. This strategy, while building on known parallel techniques, is applied here for the first time in this specific context of circuit simulation, as detailed in the paper. The algorithm was implemented in C++ using OpenMP and tested on various input matrices, showing improved performance over sequential s.

In addition to parallelization, the team proposed a partial system reduction technique that simplifies the matrix before starting iterative simulations. This approach identifies time-varying entries in the circuit, such as variable resistors, and reduces the system order by applying row operations only to constant entries, avoiding operations that would invalidate future time-dependent calculations. ensures that variable terms remain intact and are not introduced to other entries, maintaining correctness. For example, in a test circuit with a variable resistor, partial reduction allowed solving the system with fewer operations per iteration, as demonstrated in the paper's .

The experimental , conducted on a laptop with an Intel Core i7-4700HQ CPU, reveal substantial gains. On randomly generated dense matrices, the parallel algorithm achieved up to a 3.6 times speedup with eight threads for a 512×513 matrix, though efficiency decreased on larger matrices. For circuit-based sparse matrices, parallel performance improved with size, peaking at a 2.5 times speedup for a 2040×2041 matrix. Partial reduction alone cut simulation times dramatically: on circuit matrices, a 50% reduction led to time savings of 81–97%, with the largest matrix solving in 33.9 milliseconds compared to 1.078 seconds without reduction. Combining both s maintained or improved parallel efficiency on medium and large matrices, with the largest circuit matrix seeing a 3.6 times speedup after reduction.

These advancements have immediate for electronics design and education, enabling faster prototyping of devices like smartphones and medical equipment. By reducing simulation times, engineers can iterate more quickly, lowering costs and accelerating innovation. s also support educational tools, helping students visualize circuit behavior without physical components. The paper notes that the approaches are mutually independent and can be tailored to different circuit types, though performance varies with matrix density and size.

Despite the promising , the study acknowledges limitations. Parallel efficiency was not consistently maintained across all matrix sizes, particularly for smaller sparse matrices where scheduling issues caused slowdowns. The tests were run on a specific hardware setup, and performance may differ on other systems. Future work aims to extend the simulation to include reactive components like capacitors and inductors using Thévenin’s theorem, potentially broadening applicability. The researchers also plan to develop an educational simulator, but current s rely on linear systems and may not handle all circuit complexities without further adaptation.