New Method Cuts Chip Design Time by Factor

Designing the electronic chips that power everything from smartphones to medical devices is notoriously slow and expensive, often taking months of manual work. A new study demonstrates a system-level approach that can slash this time dramatically, enabling engineers to explore hardware and software options quickly without building physical prototypes. This could accelerate the development of more efficient and affordable electronics for consumers.

The researchers applied the SpecC methodology to redesign a PCM-to-PWM converter, a core component in Class-D audio amplifiers known for high efficiency. They discovered that by modeling the system at a high abstraction level, they could evaluate different hardware-software partitions to meet performance constraints while reducing costs. Specifically, they found a co-design configuration that satisfied real-time processing requirements—keeping audio playback under 4.3 seconds for a sample file—while cutting the estimated hardware cost compared to an all-hardware implementation. For instance, one option achieved a timing of 3620.6 milliseconds at a cost of $14.20, outperforming purely hardware-based solutions that were more expensive.

The team used the SpecC System-on-Chip Environment (SCE) to model the converter, starting with an untimed specification written in SpecC language. They divided the system into behaviors representing key functions like upsampling and noise shaping, then estimated execution times and costs for various hardware components, such as microprocessors and FPGAs. Through design space exploration, they mapped these behaviors to different processing elements, analyzing trade-offs between speed and expense. The process involved automatic transformations for scheduling and communication, allowing rapid simulation and validation without detailed low-level coding.

Results showed that the system-level flow provided actionable insights early in the design phase. For example, the exploration revealed that mapping the heaviest behavior (S3) to hardware met timing constraints at a reasonable cost, as detailed in Table IV of the paper. The approach also highlighted that a full-software solution on a DSP failed due to excessive execution time (over 4.5 seconds), while co-design options balanced performance and affordability. Figure 8 illustrated per-behavior execution times, confirming that a mixed hardware-software setup could achieve the goal. Compared to a traditional register-transfer level (RTL) flow, the SpecC method required less remodeling effort—taking about 31 minutes for specification and communication models—and reused existing code, reducing lines from roughly 10,000 in Verilog to 800 in SpecC/C.

This methodology matters because it addresses the growing complexity of semiconductor designs, which demand faster time-to-market and lower costs. In practical terms, it means companies could develop chips for audio devices, IoT sensors, or other consumer electronics more efficiently, potentially leading to cheaper and more innovative products. By enabling early validation and cost-performance trade-offs, the approach helps avoid costly mistakes late in development, benefiting industries reliant on custom hardware.

However, the study notes limitations, including the absence of automatic partitioning algorithms, a limited set of metrics, and an incomplete processing-element library in the SCE tool. These gaps, acknowledged as part of a beta version, mean that further refinements are needed for broader application. The paper also emphasizes that while the converter's moderate complexity made it amenable to this flow, highly intricate systems might require additional tool enhancements.